1. Field of the Invention
The present invention relates to an information processing device, and more particularly, it relates to an information processing device which is capable of executing read/write operations of a plurality of data items (or load/store operations for a plurality of operands) simultaneously.
2. Description of the Prior Art
Traditionally, in conventional data processing devices, it is well known that there are pipelined data processing devices in which an instruction fetch step and an instruction execution step are divided into a plurality of pipelined stages and these stages are pre-controlled in execution in order to decrease an instruction execution time period.
FIG. 11 is a block diagram showing a configuration of a conventional information processing device 1100 using this pipelined method. In the same diagram, the information processing device 1100 comprises an instruction register (IR) 3, a decoder (DEC) 5 for receiving data in the IR 3 and for generating various types of control signals, a sign extension section (EXT) 7 for an extension of the sign of a displacement data item in the data stored in the IR 3, a general purpose register (GR) 9, a selector (SEL) 11 for selecting one of a data item stored in the GR 9 and an output data item in the EXT 7 based on the control signal transferred from the DEC 5, an arithmetic logic unit (ALU) 15, a memory address register (MAR) 23 for latching an address data item generated by the ALU 15, a memory data register for latching a data item which is read out from a memory (not shown), an address bus (ABSU) 29 through which an address calculated and generated by the ALU 15 is transferred to the memory (not shown), and an data bus (DBUS) 31 through which required data stored in the memory is received from the memory (not shown).
The control signals generated by the DEC 5 are transferred to the GR 9 as a control signal GRC, the SEL 11 as a control signal SELC, and the ALU 15 as a control signal ALUC (each control line through which each control signal is transferred is designated by one line in FIG. 11 for brevity.).
Next, an operand load operation of the conventional information processing device 1100 having the configuration shown in FIG. 11 will be explained. The operand load operation is divided into a plurality of pipelined stages. We will explain each pipelined stage for the operand load operation.
First, in an IF (instruction fetch) stage, an instruction on an instruction bus is fetched by the IR 3. In the following ID (instruction decode) stage, the instruction in the IR 3 is decoded, and then the various control signals, a control signal GRC for the GR 9, a control signal SELC for the SEL 11, a control signal ALUC for the ALU 15, and the like used for an address calculation are generated and transferred. In addition, the data stored in the GR9 is transferred to the ALU 15. The ALU 15 receives two data items transferred from the GR 9 and the EXT 7. The data from the EXT 7 is selected by the control signal SELC transferred from the DEC 5.
Next, in the EX (execution) stage, the ALU 15 receives both the outputs from the GR9 and the EXT 7 and then performs an address calculation based on the control signal ALUC and generates (or calculates) an memory address. After the completion of this pipelined stage, the MAR 23 latches an memory address transferred from the ALU 15. In a following memory access (MA) stage, the memory address is sent to the bus ABUS 29 in order to perform a memory access operation.
Because a data item which has been read from the memory is on the bus DBUS 31, the data item is latched by the MDR 27. In a final WB (write back) stage, the data item from the MDR 27 is transferred to the GR9.
As described above in detail, in the conventional information processing device 1100 having the configuration shown in FIG. 11, because only one read/write operation for one data item per one cycle is carried out, it must be required to perform a plurality of operation times of the above read-out/write-in operations for a plurality of data items. It will take more time for the conventional information processing device to perform instructions.
In order to avoid this drawback of the conventional information device 1100 described above, there is a conventional information processing device 1200 having a configuration which is capable of reading two data items per one cycle.
FIG. 12 is a block diagram showing the configuration of the conventional information processing device 1200 as the second conventional example.
The difference between the conventional information processing device 1100 and the conventional information processing device 1200 is that the following circuit components are further incorporated in the information processing device 1200 in order to read data items simultaneously: an arithmetic logic unit (ALU) 15b; an input latch 13 for the ALU 15b; a memory access register (MAR) 23a and a MAR 23b; and a control circuit (not shown) which is incorporated in DEC 5.
When these circuit components are built into the configuration of the information processing device 1100, two data items can be read under a predetermined control.
Next, the operation of the conventional information processing device 1200 will be explained. Although the configurations of both devices 1100 and 1200 are different, this operation of the device 1200 is basically the same as that of the conventional information processing device 1100.
In the EX stage, an address calculation is performed by the ALU 15a and ALU 15b based on the control signal ALUC, so that the ALU 15a and ALU 15b generate two memory addresses. As a result, two data items can be read per one cycle simultaneously in the memory accessing (MA) stage.
Although it can read two data items per one cycle in the configuration of the information processing device 1200 described above, it must further require the added circuit components such as the ALU 15b, the input latch 13b, MAR 23b, MDR 27b in addition to the configuration of the information processing device 1100.
Because the hardware components added into the information processing device 1200 become greater than the circuit components in the information processing device 1100, it is difficult to comply with needs and requirements such as a miniaturization and a light-weight requirement and electric power is consumed more in the information processing device 1200 than that of the information processing device 1100. This is a problem.